1. Field of the Invention
The present invention relates to high density memory devices, and particularly to memory devices in which multiple planes of memory cells are arranged to provide a three-dimensional 3D array.
2. Description of Related Art
As critical dimensions of devices in integrated circuits shrink, designers have been looking to techniques for stacking multiple planes of memory cells to achieve greater storage capacity, and to achieve lower costs per bit. In one technology, a plurality of conductive planes of conductors is intersected by an array of conductive pillars. Individual memory cells are selected by selecting the corresponding pillar and conductive plane. These technologies, however, require a rectifier or diode at each memory cell in the array, which complicates the manufacturing processes and increases costs. See, for example, U.S. Patent Application Publication No. US 2010-0270593-A1 entitled Integrated Circuit 3d Memory Array And Manufacturing Method.
It is desirable to provide a structure for three-dimensional integrated circuit memory with a low manufacturing cost, including reliable, very small memory elements.